Integrated circuit (IC) semiconductor chips are the critical components found in virtually all modern telecommunications, computer, and electronics products. Many of these semiconductor chips are custom-made and tailored to the exact specifications supplied by the designers. However, these custom chips can be quite expensive to produce, and thus not ideally suited for those instances where only a limited quantity of chips are desired. Furthermore, it can take quite a long time to fabricate these custom chips. In today's competitive environment, time-to-market is of utmost importance. Moreover, if there is an error somewhere in the initial design or layout, more delays are incurred in fixing the problems.
In response to the shortcomings inherent to custom IC chips, field-programmable gate arrays (FPGAs) were developed. An FPGA is a standard off-the-shelf semiconductor chip that can be individually programmed to perform the desired functions. FPGAs can be reprogrammed an unlimited number of times and can be used in innovative designs where hardware is changed dynamically, or where hardware must be adapted to different user applications. An FPGA is typically comprised of three major configurable elements: configurable logic blocks (CLBs), input/output blocks (IOBs), and an interconnect network. The CLBs provide the functional elements for constructing the desired logic. The IOBs provide the interface between the package pins and internal signal lines. And the interconnection resources provide routing paths, programmable intersection points, and switch matrices to transfer the input and output signals of the CLBs and IOBs onto the appropriate networks.
One of the most basic building blocks of an FPGA is known as a "gate". A gate is typically comprised of a transistor that can either be turned on to conduct an electrical signal or turned off so that the electrical signal is not conducted through the transistor. In this manner, gates can be programmed to route electrical signals according to the dictates of a user. These gates can also be used in various combinations to perform logic functions on the electrical signals according to the specifications supplied by the user.
FIG. 1 shows a prior art circuit of how a gate 101 is used to coupled a signal on either of the local lines 102 and 103 onto a long line 104. Memory cell 105 controls transistors 106 and 107 to select either the IN1 signal on line 102 or the IN2 signal on line 103 to be input to buffer 108. Memory cell 105 is comprised of static memory (e.g., SRAM). Buffer 108 drives the selected signal. Gate 101 determines whether to pass that signal onto longline 104. Gate 101 also acts to isolate the longline 104 from the local lines 102 and 103. Another memory cell 109 is used to control gate 101. If the Q output from-memory cell 109 is low (e.g., 0 volts), the signal from buffer 108 is not conducted onto longline 104. A high Q output (e.g., +5 volts) causes the signal from buffer 108 to be routed onto longline 104.
Oftentimes, it is desirable to test the signal paths and gates to ensure that they are properly working. The simplest method for accomplishing this is to configure the FPGA to specifically target the signal path and gate under test. Next, a test signal is injected, and the output is monitored. However, in order to test a different gate, one needs to enter a new configuration corresponding to the new gate and signal path being tested, inject the test signal, and monitor the output signal. Clearly, repeating this testing procedure for each gate is extremely cumbersome and time-consuming, especially if one wishes to test numerous gates.
A faster approach is to test the various gates and signal paths on an interactive basis. This is accomplished by adding two transistors 110 and 111 and using three test signals: Test Mode (TM), Test Mode Bar (TMB), and Test Tri-State (TESTTS). If the TM signal is set high, this causes transistor 111 to conduct the TESTTS signal onto node 112. Simultaneously, the TMB signal causes transistor 110 to cut off the Q output signal of memory cell 109 from reaching node 112. As a result, gate 101 is controlled by the TESTTS signal and not the Q signal from memory cell 109. Thereby, one can use the TESTTS signal to test the signal path from a local interconnect line (e.g., lines 102 or 103), through a gate (e.g., transistor 101), and to a longline (e.g., line 104).
However, serious problems arise due to the fact that there is an inherent body-effected threshold voltage drop, VTN, associated with the n-channel transistor 101. This voltage drop can cause serious problems with circuits that are subsequently coupled onto longline 104.
One approach to overcoming this potential problem involves the use of "native=P" transistors which are well known in the art and therefore are not explained herein. These native transistors have higher threshold voltages than conventional transistors. Hence, the native transistors are less susceptible to the voltage drops inherent across the gates. However, one sacrifices speed when using these native transistors because it takes a longer time for these native transistors to switch on and off. Another approach has been to use "transmission" gates which are also well known to those in the art. However, each transmission gate requires an additional p-channel transistor as well as an additional inverter. Therefore, using transmission gates increases the size of a die. Increasing the die size directly translates into higher manufacturing costs because less dies (i.e., chips) can be fabricated per wafer.
A more cost-effective solution involves using a voltage pump to increase the supply voltage to the memory cells and gates. For example, instead of supplying the traditional 5 volts, a voltage pump can be used to increase an auxiliary supply voltage to 7 volts. This pumped voltage approach works fine for static memory cells in the ordinary functionality of the FPGA where they switch once and stay at their particular levels. However, pumped voltage memory cells are far too slow to function in a dynamic mode for testing purposes. Hence, a need arises for a testing circuit that is capable of being dynamically driven at the higher pumped voltage levels.